Digital Logic Gates Logic Gate

Digital Logic NOT Gate

October 13, 2018



The NOT gate could be a single input single output gate. The semiconductor should be saturated “ON” for associate inverted output “OFF”, and input is “OFF” output is should be inverted “ON”. therefore this gate is additionally referred to as-as ‘Digital Inverter’.A simple 2-input logic NOT gate is made exploitation RTL Resistor-transistor switches as shown below with the input connected on to the semiconductor base. Logic gates area unit the essential building blocks of digital logic circuits yet as digital natural philosophy.

NOT-Gate-Symbol

Fig: NOT Gate Symbol

 

The image of the not gate may be a triangle with a bubble on its finish. We know the NOT gate is the associate degree electrical converter, that inverts or reverses the input.. therefore the output is pictured by, bar image of the input.



This inversion of the input isn’t restricted to the NOT gate solely, however, is used on any digital circuit OR gate as shown with the operation of inversion being precisely the same whether or not on the input or output terminal. the simplest means is to consider the bubble as merely associate degree electrical converter.

NOT-Gate-truth-table

          Fig: NOT Gate truth table

 

That means for top logic signal input, the output of the NOT gate is going to be LOW, similarly, for low logic signal input the output of NOT gate is going to be HIGH. Logic NOT gates gives the complement of their input and square measure therefore known as-as a result of once their input is “HIGH” and output is “LOW”. This inversion of the input isn’t restricted to the NOT gate solely,



however, is used on any digital circuit OR gate as shown with the operation of inversion being precisely the same whether or not on the input or output terminal.

NOT-Gate-Diagram

Fig: NOT Gate Diagram

Here we have a tendency to connect associate alterable switch with the NOT gate and therefore the output of NOT gate is connected associate device which can ON and off once it receives high voltage and low voltage severally. during this scenario, the output voltage is measured as +5 V, which can be thought-about as a HIGH logic level. Similarly, once the high-level voltage +5 V is connected to the input, then the junction transistor is ON. therefore the total offer current is drawn by the junction transistor. this implies the provision voltage +5 V is measured at the output port, that is taken into account because of the HIGH state.

 

NOT Gate Tutorial watch the video

 

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